1. Field of the Invention
The present invention is directed in general to the field of semiconductor fabrication and integrated circuits. In one aspect, the present invention relates to complementary metal oxide semiconductor (CMOS) field effect transistors (Fêtes) fabricated with strained semiconductor channel regions
2. Description of the Related Art
CMOS devices, such as NMOS or PMOS transistors, have conventionally been fabricated on semiconductor wafers with a surface crystallographic orientation of (100), and its equivalent orientations, e.g., (010), (001), (00-1). The devices may be fabricated with a <100> crystal channel orientation (i.e., on 45 degree rotated wafer or substrate). The channel defines the dominant direction of electric current flow through the device, and the mobility of the carriers generating the current determines the drive performance of the devices. While it is possible to improve carrier mobility by intentionally stressing the channels of NMOS and/or PMOS transistors, it is difficult to simultaneously improve the carrier mobility for both types of devices formed on a uniformly-strained substrate because PMOS carrier mobility and NMOS carrier mobility are optimized under different types of stress. For example, those skilled in the art have discovered that electron mobility for NMOS devices having <100> oriented channels may be improved by intentionally implementing a tensile stress in NMOS transistor channels to improve carrier mobility, but PMOS devices are insensitive to any uneasily stress in the channel direction. Some CMOS device fabrication processes have addressed the different requirements by fabricating different stress layers for the NMOS and PMOS devices, but this adds processing complexity to the fabrication, especially where separate masking is required for formation of the NMOS and PMOS devices. Moreover, the selection of stress conditions for each type of device is complicated by the fact that stress conditions that optimize carrier mobility may negatively impact other device characteristics, such as threshold voltage, thereby.
To avoid processing complexity, other CMOS device fabrication processes have applied a single tensile contact etch stop layer over both NMOS and PMOS devices fabricated on substrates with <100> channel orientation. While this approach improves the NMOS device mobility, it provides relatively little strain enhancement for the PMOS devices, and does not provide a mechanism for addressing channel directivity or interface trap density (DIT) in the PMOS devices. This approach can also result in the formation of voids when the tensile contact etch stop layer is deposited over the closely spaced transistor structures. This is shown in FIG. 1 which illustrates a partial cross-sectional view of a semiconductor wafer structure 100 in which a single tensile contact etch stop layer 105 is formed over a plurality of closely-spaced transistor structures (including gates 102, spacers 103 and source/drain regions 104 formed in the substrate 101), where the reduced spacing between transistor structures (due in part to the relatively wide spacers 103) causes voids 106 to be formed in the tensile contact etch stop layer 105.
Accordingly, there is a need for improved semiconductor processes and devices to overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.